This invention relates to a semiconductor memory device having a plurality of semiconductor memory cells, and techniques for semiconductor memory cells; and more particularly, in one aspect, to techniques and circuitry for reading data that is stored in memory cells including techniques and circuitry for generating a reference current which is used to read data that is stored in memory cells, of a semiconductor dynamic random access memory (“DRAM”) device, wherein, for example, the memory cells have an electrically floating body in which an electrical charge is stored.
There are many different types and/or forms of DRAM cells, including, for example, a semiconductor memory cell consisting of an access transistor and a capacitor, which stores an electric charge representing a bi-stable memory state. The binary logic state stored in the capacitor of each cell is determined by comparing an output voltage of the memory cell with a reference voltage (for example, Vdd/2). The access transistor serves as a switch for controlling the charging and discharging of the capacitor as well as reading and writing of the logic states into the capacitor (i.e., charging or discharging the capacitor). (See, for example, U.S. Pat. No. 6,717,835).
Another type of dynamic random access memory cell is described and illustrated in non-provisional patent application entitled “Semiconductor Memory Device”, which was filed on Jun. 10, 2003, and assigned Ser. No. 10/450,238 (hereinafter “Semiconductor Memory Device Patent Application”). With reference to FIGS. 1A and 1B, the Semiconductor Memory Device Patent Application discloses, among other things, semiconductor memory device 10 in which each memory cell 12 consists of transistor 14 having gate 16, body region 18, which is electrically floating, source region 20 and drain region 22. The body region 18 is disposed between and adjacent to source region 20 and drain region 22. Data is written into or read from a selected memory cell by applying suitable control signals to a selected word line(s) 24, a selected source line(s) 26 and/or a selected bit line(s) 28. In response, charge carriers are accumulated in or emitted and/or ejected from electrically floating body region 18 wherein the data states are defined by the amount of carriers within electrically floating body region 18. Notably, the entire contents of the Semiconductor Memory Device Patent Application, including, for example, the features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are incorporated by reference herein.
In particular, in one embodiment, the memory cell of the Semiconductor Memory Device Patent Application operates by accumulating in or emitting/ejecting majority carriers (electrons or holes) 30 from body region 18 of, for example, N-channel transistors. (See, FIGS. 2A and 2B). In this regard, accumulating majority carriers (in this example, “holes”) 30 in body region 18 of memory cells 12 via, for example, impact ionization near source region 20 and/or drain region 22, is representative of a logic high or “1” data state. (See, FIG. 2A). Emitting or ejecting majority carriers 30 from body region 18 via, for example, forward biasing the source/body junction and/or the drain/body junction, is representative of a logic low data state (“0 or A0”). (See, FIG. 2B).
Several techniques may be implemented to read the data stored in (or write the data into) the memory cell. For example, a current sense amplifier may be employed to read the data stored in memory cells. In this regard, a current sense amplifier may compare the cell current to a reference current, for example, the current of a reference cell. From that comparison, it may be determined whether memory cell contained a logic high data state (relatively more majority carriers contained within body region) or logic low data state (relatively less majority carriers contained within body region). The differences of the charge stored in the body of the transistor affects the threshold voltage of the transistor, which in turn affects the current conducted by the transistor when switched into its conductive state.
In particular, with reference to FIG. 3, sense amplifier 32 (for example, a cross-coupled sense amplifier) compares the current conducted by transistor 14 of memory cell 12 with a reference current generated by reference current generator 34. The magnitude of the reference current generally lies between the magnitudes of the currents conducted in the logic high data state and logic low data state of memory cell 12. The sense amplifier 32 compares the reference current to the current produced by memory cell 12 (the current varies depending on whether memory cell 12 is either in a logic high data state or logic low data state). Based on that comparison, sense amplifier 32 generates or outputs an output signal (on output 36) having a positive or negative polarity, depending upon whether memory cell 12 stored a logic high or logic low binary data state.
With reference to FIG. 4, a conventional reference current generator includes transistor 38, which stores a logic high data state, and transistor 40, which stores a logic low data state. The reference current generator 34 also includes switches 44 (comprised of, for example, transistors) which selectively connect transistors 38 and 40 to node 42. In addition, switches 44 may selectively isolate transistors 38 and 40 to enable data states to be written into transistors 38 and 40. During a read operation, switches 44 are closed to connect transistors 38 and 40 to node 42.
With continued reference to FIG. 4, reference current generator 34 further includes cascade current source 46 which includes PMOS transistor 48 having its gate connected to its source, in series with NMOS transistor 50, the source of which is connected to node 42. The gate bias voltage of NMOS transistor 50 is controlled by connecting node 42 to the inverting input of operational amplifier 52. The output of operational amplifier 52 is connected to the gate of NMOS transistor 50. The non-inverting input of operational amplifier 52 is supplied with a reference voltage (VBLR).
The total current passing through node 42 (ignoring the negligible input current of operational amplifier 52) may be characterized as the sum of the currents passing through transistors 38 and 40, (i.e., the sum of the currents conducted by transistors 38 and 40 having a logic high data state and a logic low data state, respectively). In operation, the current passing through node 42 adjusts the voltage of node 42, which in turn adjusts the gate-source voltage of NMOS transistor 50 until the current (2Iref) supplied by cascade current source 46 equals to the sum of the currents flowing through transistors 38 and 40.
Conventional reference current generators (for example, reference current generator 34 of FIGS. 3 and 4) tend to “track” changing characteristics of memory cell 12, for example, changes induced by temperature variations and/or aging of the transistors, in a relatively slow manner. In addition, reference current generator 34 often has a high noise correlation with memory cell 12. In this regard, rapid voltage changes (for example, voltage spikes) on the gate, drain, source or silicon on insulator back gate voltage of memory cell 12 will also be imposed or replicated on transistors 38 and 40. As such, the difference between the current of memory cell 12 and the reference current tend to remain largely unchanged.
However, the reference current generator configuration of FIGS. 3 and 4 suffers from a drawback that the charge state of transistors 38 and 40 decays over time. (See, FIG. 5). As a result, the magnitude of the reference current also changes overtime (for example, decays over time). In this regard, the reference current varies throughout its refreshing cycle between a value “Ref1” at the beginning of a refreshing cycle, and “Ref2” at the end of the cycle. Accordingly, the charge states of transistors 38 and 40 must be periodically refreshed. Notably, transistors 38 and 40 should be refreshed at least as often as that of memory cell 12 in order to ensure proper operation.
In addition, such a conventional configuration also suffers from the disadvantage that the transistors 38 and 40 may often be at a different stage of refresh cycles relative to memory cell 12. This is particularly disadvantageous in the case illustrated in FIG. 5, in which reference transistors 38 and 40 are newly or recently refreshed (i.e., references near the beginning of the cycle, indicated in FIG. 5 as 54) and transistor 14 of memory cell 12 is near the end of its cycle prior to refreshing. Under this circumstance, when transistor 40 provides a current (representative of a decayed data state) that is equal to the reference current (indicated in FIG. 5 as 56), sense amplifier 32 may have difficulty, or may no longer be capable of, distinguishing between logic low data state and a logic high data state. In this way, a data reading uncertainty arises.
Notably, in sense amplifier 32 of the conventional-type, offset currents and/or voltages may arise because of transistor mismatch. Furthermore, the parasitic capacitances of the interconnection traces or wires as well as the storage cells themselves may neither be perfectly matched. These effects limit the accuracy with which the magnitude of the reference signal can be chosen between the magnitude of the signals representing the logic high data state and the logic low data states. This is particularly problematic in integrated memory devices of very small transistor size, even if the memory device consists of generally identical transistors.